Si4322
FIFO Buffered Data Read
In this operating mode, incoming data are clocked into a 48 bit FIFO buffer. The receiver starts to fill up the FIFO when the Valid Data
Indicator (VDI) bit and/or the synchron word recognition circuit indicates potentially real incoming data. This prevents the FIFO from
being filled with noise and overloading the external microcontroller.
For further details see the Receiver Setting Command and the Output and FIFO Command .
Polling Mode:
The nFFS signal selects the buffer directly and its content could be clocked out through pin SDO by SCK. Set the FIFO IT level to 1. In
this case, as long as FFIT indicates received bits in the FIFO, the controller may continue to take the bits away. When FFIT goes low,
no more bits need to be taken. An SPI read command is also available.
Interrupt Controlled Mode:
The user can define the FIFO level (the number of received bits) which will generate the nFFIT when exceeded. The status bits report
the changed FIFO status in this case.
FIFO Read Example with FFIT Polling:
nSEL*
0
1
2
3
4
SCK
nFFS**
FIFO read out
SDO
FIFO OUT
FO+1
FO+2
FO+3
FO+4
FFIT
NOTE:
*nSEL is used to activate SDO
**nFFS is used to select FIFO
During FIFO access the f SCK cannot be higher than f ref /4, where f ref is the crystal oscillator frequency.
Power Saving Modes
The different operating modes of the chip depend on the following control bits:
eb or et
en
ex
Operating Mode
Active
Idle
Sleep
Standby
(Configuration
Setting Comand)
X
X
1
0
(Receiver Setting
Command
1
0
0
0
(Configuration
Setting Command)
1
1
0
0
17
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